This invention relates generally to clock pulse generating circuits constituted in the form of shift registers, and more particularly, to a clock pulse generating circuit of the shift register type for producing multiphase clock pulses used for driving a charge transfer device which is adapted to be driven in the manner of electrode-per-bit clocking.
Multiphase clock pulses are necessitated for driving a charge transfer device adapted to be driven by the electrode-per-bit clocking. In the case of such electrode-per-bit clocking for the charge transfer device, as shown in FIG. 1, multiphase clock pulses V.sub.1, V.sub.2, V.sub.3, - - - each having a pulse width .tau..sub.1 and being supplied to the charge transfer device are required not to have overlapping portions but to have a time interval .tau..sub.2 between each two of them appearing sucessively. Further, for increasing the transfer efficiency to the utmost, it is desirable that the pulse width .tau..sub.1 and the time interval .tau..sub.2 are capable of being varied in response to clock pulses supplied from the outside without varying a time interval .tau..sub.1 +.tau..sub.2 between rising edges or falling edges of each successively appearing two of the pulses V.sub.1, V.sub.2, V.sub.3, - - - .
There has been proposed a pulse generating circuit for producing multiphase clock pulses, which is constituted in the form of a shift register, as shown in FIG. 2.
In the circuit of FIG. 2, circuit blocks 1, 2, 3, - - - , in each of which a switching element S and a capacitive element C are connected in series with each other and a voltage obtained at the connecting point between the switching element S and the capacitive element of C is supplied to an inverter I, are connected successively to form a plurality of stages in such a manner as that an output end of the inverter I in one of them is coupled to the series connection of the switching element S and the capacitive element C in the next one of them. Further, an output end of an inverter I.sub.0 is connected to the series connection of the switching element S and the capacitive element C in the circuit block V.sub.1 at the first stage and a starting signal .phi..sub.0 is supplied to the inverter I.sub.0. The switching elements S in the circuit blocks 1, 3, 5, - - - at the odd stages are controlled to be turned on or off by a first timing signal .phi..sub.1, while the switching elements S in the circuit blocks 2, 4, 6, - - - at the even stages are controlled to be turned on or off by a second timing signal .phi..sub.2.
In more detail, the switching element S is formed with an insulated gate field effect transistor of the enhancement type with its gate to which the first or second timing signal .phi..sub.1 or .phi..sub.2 is supplied. Each of the inverters I.sub.0 and I is formed with an insulated gate field effect transistor of the enhancement type E and an insulated gate field effect transistor of the depletion type D with its gate and source connected to the drain of the field effect transister E. The gate of the field effect transister E is supplied with the starting signal .phi..sub.0 or the voltage obtained at the connecting point between the switching element S and the capacitive element C, and the drain of the field effect transistor E is used as an output terminal.
Each of the first and second timing signals .phi..sub.1 and .phi..sub.2 is composed of positive pulses having a constant cyclical period .tau..sub.3, and a period of each pulse taking a high level by which the switching element S is turned on in the timing signal .phi..sub.1 is not coincident with a period of each pulse taking a high level by which the switching element S is turned on in the timing signal .phi..sub.2, as shown in FIG. 3. That is, the timing signals .phi..sub.1 and .phi..sub.2 are different in phase from each other. The starting signal .phi..sub.0 is formed into positive pulses having a cyclical period sufficiently longer than the cyclical period .tau..sub.3 of each of the first and second timing signals .phi..sub.1 and .phi..sub.2, and a period of each positive pulse taking a high level and forming the starting signal .phi..sub.0 includes one of the periods of the pulses forming the first timing signal .phi..sub.1.
In this circuit, the field effect transistor E in the inverter I.sub.0 is made conductive and therefore the output voltage of the inverter I.sub.0 takes a ground level during the period of the pulses of the starting signal .phi..sub.0. Within the period of the pulse of the starting signal .phi..sub.0, when the first timing signal .phi..sub.1 rises to the high level from the low level, the switching element S in the circuit block 1 at the first stage is turned on and the voltage across the capacitive element C in the circuit block 1 takes the ground level, so that the field effect transistor E forming the inverter I in the circuit block 1 is turned off and therefore the output voltage V.sub.1 ' of the circuit block 1 takes the level of a voltage source +V.sub.CC. This condition is maintained, after the first timing signal .phi..sub.1 falls to the low level from the high level and switching element S in the circuit block 1 is turned off, up to an instant at which the first timing signal .phi..sub.1 rises again to the high level from the low level. Before the first timing signal .phi..sub.1 rises again to the high level from the low level, when the second timing signal .phi..sub.2 rises to the high level from the low level, the switching element S in the circuit block 2 at the second stage are turned on and the voltage across the capacitive element C in the circuit block 2 takes a level almost equal to the level of the voltage source +V.sub.CC, so that the field effect transistor E forming the inverter I in the circuit block 2 is turned on and therefore the output voltage of the circuit block 2 takes the ground level.
Then, when the first timing signal .phi..sub.1 rises again to the high level from the low level, the switching element S in the circuit block 1 at the first step is again turned on. On this occasion, since the field effect transistor E forming the inverter I.sub.0 has been turned off and the output voltage of the inverter I.sub.0 takes the level of the voltage source +V.sub.CC, the voltage across the capacitive element C in the circuit block 1 takes the level almost equal to the level of the voltage source +V.sub.CC and therefore the field effect transistor E forming the inverter I in the circuit block 1 is turned on, so that the output voltage V.sub.1 ' of the circuit block 1 takes the ground level. Simultaneously, the switching element S in the circuit block 3 at the third stage is turned on. On this occasion, the switching element S in the circuit block 2 has been turned off and the voltage across the capacitive element C in the circuit block 2 is maintained to take the level almost equal to the level of the voltage source +V.sub.CC even though the output voltage V.sub.1 ' of the circuit block 1 takes the ground level. Further, since the field effect transistor E forming the inverter I in the circuit block 2 is conductive and the output voltage of the circuit block 2 takes the ground level, the voltage across the capacitive element C in the circuit block 3 takes the ground level and therefore the field effect transistor E forming the inverter I in the circuit block 3 is turned off, so that an output voltage V.sub.2 ' of the circuit block 3 takes the level almost equal to the level of the voltage source +V.sub.CC.
After that, the circuit operates continuously in the same manner as mentioned above and the output voltages V.sub.1 ', V.sub.3 ', V.sub.5 ', - - - having respective identical periods of the high level, which do not overlap between each two appearing successively, are obtained from the circuit blocks 1, 3, 5, - - - positioned at the first, third, fifth, - - - stages, respectively, as multiphase clock pulses. However, as apparent from FIG. 3, the period of each of these pulses V.sub.1 ', V.sub.3 ', V.sub.5 ', - - - is set to coincide with a period from one rising edge to the next rising edge of the first timing signal .phi..sub.1, that is, the cyclical period .tau..sub.3 of the first timing signal .phi..sub.1 and therefore therein no time interval between each successively appearing two of them.
Accordingly, if it is intended to obtain multiphase clock pulses having a predetermined time interval between each two of them appearing successively from the pulses generating circuit as mentioned above, it is necessary to derive the output voltages V.sub.1 ', V.sub.5 ', - - - from the circuit blocks 1, 5, - - - positioned at the first, fifth, - - - stages. That is, the output voltages are derived every four circuit blocks to produce the multiphase clock pulses.
However, when such a pulse generating circuit in which the output voltages from every four circuit blocks are derived to produce multiphase clock pulses is used for generating n phase clock pulses, the pulse generating circuit must be constituted to contain {1+4(n-1)} circuit blocks each composed of the switching element S, capacitive element C and inverter I, and consequently, have to employ a great number of circuit elements. Besides, in such case, since both a pulse width of each of the n phase clock pulses and a time interval between rising edges or falling edges of successively appearing two of them are determined by the cyclical period .tau..sub.3 of the first timing signal .phi..sub.1, it is impossible to vary the pulse width of each of the n phase clock pulses without varying the time interval between the rising edges or falling edges of successively appearing two of them.